AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 20

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

CE# Control in Linear Mode
T h e C E # ( C h i p E n a b l e ) p i n e n a b l e s t h e
Am29BDD160 during read mode operations. CE#
must meet the required burst read setup times for
burst cycle initiation. If CE# is taken to V
time during the burst linear or burst cycle, the device
immediately exits the burst sequence and floats the
DQ bus and IND/WAIT# signal. Restarting a burst
cycle is accomplished by taking CE# and ADV# to
V
ADV# Control In Linear Mode
T
linear burst cycle at the clock edge when CE# and
ADV# are at V
ther linear burst mode operation. A burst access is
initiated and the address is latched on the first rising
CLK edge when ADV# is active or upon a rising
ADV# edge, whichever occurs first. If the ADV# sig-
nal is taken to V
sequence, the previous address is discarded and
subsequent burst transfers are invalid until ADV#
transitions to V
a new burst sequence.
RESET# Control in Linear Mode
The RESET# pin immediately halts the linear burst
access when taken to V
IND/WAIT# signal float. Additionally, the Configura-
tion Register contents are reset back to the default
condition where the device is placed in asynchronous
access mode.
18
Thirty-Two Linear Data Transfers
IL
he ADV# (Address Valid) pin is used to initiate a
Sixteen Linear Data Transfers
.
(X16 Only)
Table 6. 16-Bit and 32-Bit Linear and Burst Data Order (Sheet 2 of 2)
IL
IH
IL
and the device is configured for ei-
before a clock edge, which initiates
prior to the end of a linear burst
IL
. The D Q data bus an d
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V (A3:A-1 = 00000)
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-0 (A3:A-1 = 00001)
U-V-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T (A3:A-1 = 11110)
V-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U (A3:A-1 = 11111)
IH
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F (A2:A-1/ A3-A0 = 0000)
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 (A2:A-1/ A3-A0 = 0001)
2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 (A2:A-1/ A3-A0 = 0010)
3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 (A2:A-1/ A3-A0 = 0011)
5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 (A2:A-1/ A3-A0 = 0101)
6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 (A2:A-1/ A3-A0 = 0110)
7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 (A2:A-1/ A3-A0 = 0111)
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 (A2:A-1/ A3-A0 = 1000)
9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 (A2:A-1/ A3-A0 = 1001)
A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 (A2:A-1/ A3-A0 = 1010)
B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A (A2:A-1/ A3-A0 = 1011)
C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B (A2:A-1/ A3-A0 = 1100)
D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C (A2:A-1/ A3-A0 = 1101)
E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D (A2:A-1/ A3-A0 = 1110)
F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E (A2:A-1/ A3-A0 = 1111)
4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 (A:A-1/ A3-A0 = 0100)
at any
Am29BDD160G
OE# Control in Linear Mode
The OE# (Output Enable) pin is used to enable the
linear burst data on the DQ data bus and the IND/
WAIT# pin. De-asserting the OE# pin to V
burst operation floats the data bus and the IND/
WAIT# pin. However, the device will continue to op-
erate internally as if the burst sequence continues
until the linear burst is complete. The OE# pin does
not halt the burst sequence, this is accomplished by
either taking CE# to V
pulse. The DQ bus and IND/WAIT# signal remain in
the float state until OE# is taken to V
IND/WAIT# Operation in Linear Mode
The IND/WAIT#, or End of Burst Indicator signal
(when in linear modes), informs the system that the
last address of a burst sequence is on the DQ data
bus. For example, if a 4-word linear burst access is
enabled using a 16-bit DQ bus (WORD# = V
IND/WAIT# signal transitions active on the fourth
access. If the same scenario is used, but instead the
32-bit DQ bus is enabled, the IND/WAIT# signal
transitions active on the second access. The IND/
WAIT# signal has the same delay and setup timing
as the DQ pins. Also, the IND/WAIT# signal is con-
trolled by the OE# signal. If OE# is at V
WAIT# signal floats and is not driven. If OE# is at
V
transitions to V
quence. The IND/WAIT# signal timing and duration
is (See “Configuration Register” for more informa-
tion). The following table lists the valid combinations
of the Configuration Register bits that impact the
IND/WAIT# timing.
IL
, the IND/WAIT# signal is driven at V
:
IL
indicating the end of burst se-
IH
or re-issuing a new ADV#
IL
.
IH
IH
, the IND/
IH
during a
IL
until it
), the