ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 269

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Table 106. Algorithm for Using the ADC
Note:
2490G–AVR–03/04
Ste
p
1
2
3
4
5
6
7
8
9
10
11
Actions
SAMPLE_PRELOAD
EXTEST
Verify the COMP bit scanned out to be 0
Verify the COMP bit scanned out to be 1
1. Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency. As the algorithm keeps
HOLD high for five steps, the TCK clock frequency has to be at least five times the number of scan bits divided by the maxi-
mum hold time, t
hold,max
.
As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3
when the power supply is 5.0V and AREF is externally connected to V
The recommended values from Table 105 are used unless other values are given in the
algorithm in Table 106. Only the DAC and Port Pin values of the Scan-chain are shown.
The column “Actions” describes what JTAG instruction to be used before filling the
Boundary-scan Register with the succeeding columns. The verification should be done
on the data scanned out when scanning in the data on the same row in the table.
(1)
ADCEN
The lower limit is:
The upper limit is:
1
1
1
1
1
1
1
1
1
1
1
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
DAC
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
1024 1.5V 0,95 5V
1024 1.5V 1.05 5V
⋅
⋅
HOLD
⋅
1
0
1
1
1
1
0
1
1
1
1
⋅
⁄
⁄
PRECH
1
1
1
1
0
1
1
1
1
0
1
=
=
291
323
=
Data
PA3.
=
ATmega64(L)
0
0
0
0
0
0
0
0
0
0x123
0
0
0x143
Control
CC
PA3.
0
0
0
0
0
0
0
0
0
0
0
.
Enable
PA3.
Pull-
up_
0
0
0
0
0
0
0
0
0
0
0
269