ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 168
ATMEga64L
Manufacturer Part Number
ATMEga64L
Description
8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATMEGA64L.pdf
(363 pages)
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Data Modes
168
ATmega64(L)
There are four combinations of SCK phase and polarity with respect to serial data,
which are determined by control bits CPHA and CPOL. The SPI data transfer formats
are shown in Figure 77 and Figure 78. Data bits are shifted out and latched in on oppo-
site edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is
clearly seen by summarizing Table 70 and Table 71, as done below:
Table 73. CPOL and CPHA Functionality
Figure 77. SPI Transfer Format with CPHA = 0
Figure 78. SPI Transfer Format with CPHA = 1
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB
LSB
MSB
LSB
Bit 6
Bit 1
Sample (Falling)
Sample (Rising)
Leading Edge
Setup (Rising)
Setup (Falling)
Bit 6
Bit 1
Bit 5
Bit 2
Bit 5
Bit 2
Bit 4
Bit 3
Bit 4
Bit 3
Sample (Falling)
Sample (Rising)
Bit 3
Bit 4
Setup (Falling)
Setup (Rising)
Trailing Edge
Bit 3
Bit 4
Bit 2
Bit 5
Bit 2
Bit 5
Bit 1
Bit 6
Bit 1
Bit 6
2490G–AVR–03/04
SPI Mode
LSB
MSB
0
1
2
3
LSB
MSB
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