ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 116

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Counter Unit
116
ATmega64(L)
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional
counter unit. Figure 47 shows a block diagram of the counter and its surroundings.
Figure 47. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High
(TCNTnH) containing the upper eight bits of the counter, and Counter Low (TCNTnL)
containing the lower eight bits. The TCNTnH Register can only be indirectly accessed
by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU
accesses the high byte temporary register (TEMP). The temporary register is updated
with the TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the
temporary register value when TCNTnL is written. This allows the CPU to read or write
the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is impor-
tant to notice that there are special cases of writing to the TCNTn Register when the
counter is counting that will give unpredictable results. The special cases are described
in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or dec-
remented at each Timer Clock (clk
internal clock source, selected by the Clock Select bits (CSn2:0). When no clock source
is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be
accessed by the CPU, independent of whether clk
rides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode
bits (WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and
TCCRnB). There are close connections between how the counter behaves (counts) and
how waveforms are generated on the Output Compare outputs OCnx. For more details
about advanced counting sequences and waveform generation, see “Modes of Opera-
tion” on page 122.
The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation
selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.
Count
Direction
Clear
clk
TOP
BOTTOM
T
n
TCNTnH (8-bit)
TEMP (8-bit)
TCNTn (16-bit Counter)
DATA BUS
Increment or decrement TCNTn by 1.
Select between increment and decrement.
Clear TCNTn (set all bits to zero).
Timer/counter clock.
Signalize that TCNTn has reached maximum value.
Signalize that TCNTn has reached minimum value (zero).
TCNTnL (8-bit)
(8-bit)
Direction
T
Count
Clear
n
). The clk
Control Logic
TOP
T
n
BOTTOM
can be generated from an external or
T
n
TOVn
(Int.Req.)
clk
is present or not. A CPU write over-
Tn
Clock Select
( From Prescaler )
Detector
Edge
2490G–AVR–03/04
Tn