ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 166

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

166
ATmega64(L)
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written
logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will
be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to
re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to Figure 77 and Figure 78 for an example. The CPOL func-
tionality is summarized below:
Table 70. CPOL Functionality
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to Figure 77 and Figure 78 for an example.
The CPHA functionality is summarized below:
Table 71. CPHA Functionality
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and
SPR0 have no effect on the slave. The relationship between SCK and the Oscillator
Clock frequency f
Table 72. Relationship Between SCK and the Oscillator Frequency
SPI2X
CPOL
CPHA
0
0
0
0
1
1
1
1
0
1
0
1
osc
is shown in Table 72.
SPR1
0
0
1
1
0
0
1
1
Leading Edge
Leading Edge
Sample
Falling
Rising
Setup
SPR0
0
1
0
1
0
1
0
1
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
2490G–AVR–03/04