ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 142

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Timer/Counter3,
Timer/Counter2 and
Timer/Counter1
Prescalers
Internal Clock Source
Prescaler Reset
External Clock Source
142
ATmega64(L)
Timer/Counter3, Timer/Counter2 and Timer/Counter1 share the same prescaler mod-
ule, but the Timer/Counters can have different prescaler settings. The description below
applies to all of the mentioned Timer/Counters.
The Timer/Counter can be clocked directly by the system clock (by setting the
CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock
frequency equal to system clock frequency (f
the prescaler can be used as a clock source. The prescaled clock has a frequency of
either f
The prescaler is free running, for example, it operates independently of the Clock Select
logic of the Timer/Counter, and it is shared by Timer/Counter1, Timer/Counter2, and
Timer/Counter3. Since the prescaler is not affected by the Timer/Counter’s clock select,
the state of the prescaler will have implications for situations where a prescaled clock is
used. One example of prescaling artifacts occurs when the timer is enabled and clocked
by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the
timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles,
where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution. However, care must be taken if the other Timer/Counter that shares the
same prescaler also use prescaling. A Prescaler Reset will affect the prescaler period
for all Timer/Counters it is connected to.
An external clock source applied to the Tn pin can be used as Timer/Counter clock
(clk
chronization logic. The synchronized (sampled) signal is then passed through the edge
detector. Figure 59 shows a functional equivalent block diagram of the Tn synchroniza-
tion and edge detector logic. The registers are clocked at the positive edge of the
internal system clock (
system clock.
The edge detector generates one clk
negative (CSn2:0 = 6) edge it detects.
Figure 59. Tn Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system
clock cycles from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at
least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse
is generated.
clk
T1
Tn
I/O
/clk
CLK_I/O
T2
/clk
D Q
LE
/8, f
T3
). The Tn pin is sampled once every system clock cycle by the pin syn-
CLK_I/O
/64, f
D Q
clk
I/O
). The latch is transparent in the high period of the internal
CLK_I/O
/256, or f
T1
/clk
T
CLK_I/O
2
/clk
CLK_I/O
T
3
/1024.
pulse for each positive (CSn2:0 = 7) or
). Alternatively, one of four taps from
D
Q
Edge Detector
2490G–AVR–03/04
Tn_sync
(To Clock
Select Logic)