ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 107

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Timer/Counter Interrupt Mask
Register – TIMSK
Timer/Counter Interrupt Flag
Register – TIFR
2490G–AVR–03/04
•
• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable
When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is
executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in
the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if
an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the
Timer/Counter Interrupt Flag Register – TIFR.
• Bit 1 – OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when a Compare Match occurs between the Timer/Counter0
and the data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by
writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Com-
pare Match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare
Match Interrupt is executed.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
read as the previous value (before entering sleep) until the next rising TOSC1 edge.
The phase of the TOSC clock after waking up from Power-save mode is essentially
unpredictable, as it depends on the wake-up time. The recommended procedure for
reading TCNT0 is thus as follows:
1. Write any value to either of the registers OCR0 or TCCR0.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT0.
During asynchronous operation, the synchronization of the interrupt flags for the
asynchronous timer takes three processor cycles plus one timer cycle. The timer is
therefore advanced by at least one before the processor can read the timer value
causing the setting of the interrupt flag. The Output Compare pin is changed on the
timer clock and is not synchronized to the processor clock.
OCF2
R/W
7
0
OCIE2
R/W
7
0
TOV2
R/W
TOIE2
6
0
R/W
6
0
ICF1
R/W
TICIE1
5
0
R/W
5
0
OCF1A
R/W
OCIE1A
4
0
R/W
4
0
OCF1B
OCIE1B
R/W
R/W
3
0
3
0
TOV1
R/W
TOIE1
R/W
2
0
2
0
ATmega64(L)
OCF0
OCIE0
R/W
R/W
1
0
1
0
TOV0
TOIE0
R/W
R/W
0
0
0
0
TIMSK
TIFR
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