ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 151

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

2490G–AVR–03/04
non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2
slopes represent Compare Matches between OCR2 and TCNT2.
Figure 66. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If
the interrupt is enabled, the interrupt handler routine can be used for updating the com-
pare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2
pin. Setting the COM21:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COM21:0 to three (see Table 66 on page
156). The actual OC2 value will only be visible on the port pin if the data direction for the
port pin is set as output. The PWM waveform is generated by setting (or clearing) the
OC2 Register at the Compare Match between OCR2 and TCNT2, and clearing (or set-
ting) the OC2 Register at the timer clock cycle the counter is cleared (changes from
MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR2 Register represents special cases when generating a
PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the
output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal
to MAX will result in a constantly high or low output (depending on the polarity of the out-
put set by the COM21:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved
by setting OC2 to toggle its logical level on each Compare Match (COM21:0 = 1). The
waveform generated will have a maximum frequency of f
set to zero. This feature is similar to the OC2 toggle in CTC mode, except the double
buffer feature of the Output Compare unit is enabled in the fast PWM mode.
TCNTn
OCn
OCn
Period
1
2
f
3
OCnPWM
4
=
----------------- -
N 256
f
clk_I/O
⋅
5
OC2
6
ATmega64(L)
= f
clk_I/O
OCRn Interrupt Flag Set
OCRn Update and
TOVn Interrupt Flag Set
7
/2 when OCR2 is
(COMn1:0 = 2)
(COMn1:0 = 3)
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