ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 224

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Miscellaneous States
Table 92. Miscellaneous States
224
Status Code
(TWSR)
Prescaler Bits
are 0
0xF8
0x00
ATmega64(L)
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face hardware
No relevant state information
available; TWINT = “0”
Bus error due to an illegal
START or STOP condition
Figure 103. Formats and States in the Slave Transmitter Mode
There are two status codes that do not correspond to a defined TWI state, see Table 92.
Status 0xF8 indicates that no relevant information is available because the TWINT flag
is not set. This occurs between other states, and when the TWI is not involved in a serial
transfer.
Status 0x00 indicates that a bus error has occurred during a Two-wire Serial Bus trans-
fer. A bus error occurs when a START or STOP condition occurs at an illegal position in
the format frame. Examples of such illegal positions are during the serial transfer of an
address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT is
set. To recover from a bus error, the TWSTO flag must set and TWINT must be cleared
by writing a logic one to it. This causes the TWI to enter the not addressed Slave mode
and to clear the TWSTO flag (no other bits in TWCR are affected). The SDA and SCL
lines are released, and no STOP condition is transmitted.
Reception of the own
slave address and one or
more data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
To/from TWDR
No TWDR action
No TWDR action
From master to slave
From slave to master
Application Software Response
S
STA
0
SLA
STO
No TWCR action
1
To TWCR
R
TWINT
DATA
1
$A8
$B0
A
A
n
TWEA
X
A
DATA
Next Action Taken by TWI Hardware
Wait or proceed current transfer
Only the internal hardware is affected, no STOP condi-
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-wire Serial Bus. The
prescaler bits are zero or masked to zero
$B8
A
DATA
$C0
$C8
A
A
2490G–AVR–03/04
P or S
All 1's
P or S