ATMEga64L ATMEL Corporation, ATMEga64L Datasheet - Page 143

• Manufacturer Part Number: ATMEga64L
• Description: 8-bit AVR Microcontroller with 64K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Special Function IO Register –
SFIOR
2490G–AVR–03/04
Each half period of the external clock applied must be longer than one system clock
cycle to ensure correct sampling. The external clock must be guaranteed to have less
than half the system clock frequency (f
the edge detector uses sampling, the maximum frequency of an external clock it can
detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-
ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,
resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than f
An external clock source can not be prescaled.
Figure 60. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing TSM bit to one activates the Timer/Counter Synchronization mode. In this mode,
the value that is written to PSR0 and PSR321 bits is kept, hence keeping the corre-
sponding prescaler reset signals asserted. This ensures that the corresponding
Timer/Counters are halted and can be configured to the same value without the risk of
one of them advancing during configuration. When the TSM bit written zero, the PSR0
and PSR321 bits are cleared by hardware, and the Timer/Counters start counting
simultaneously.
• Bit 0 – PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and
When this bit is one, the Timer/Counter3, Timer/Counter2, and Timer/Counter1 pres-
caler will be reset. The bit is normally cleared immediately by hardware, except if the
TSM bit is set. Note that Timer/Counter3 Timer/Counter2, and Timer/Counter1 share the
same prescaler and a reset of this prescaler will affect all three timers.
Bit
Read/Write
Initial Value
T3
Timer/Counter1
CS30
CS32
CS31
1. The synchronization logic on the input pins (T3/T2/T1) is shown in Figure 59.
TIMER/COUNTER3 CLOCK SOURCE
0
PSR321
TSM
R/W
CK
7
0
clk
T3
R
6
–
0
T2
CS20
CS22
CS21
R
5
–
0
clk_I/O
Clear
ExtClk
/2.5.
TIMER/COUNTER2 CLOCK SOURCE
0
R
4
–
0
< f
clk_I/O
10-BIT T/C PRESCALER
clk
T2
ACME
R/W
3
0
/2) given a 50/50% duty cycle. Since
PUD
R/W
T1
2
0
CS10
CS12
CS11
ATmega64(L)
PSR0
R/W
1
0
TIMER/COUNTER1 CLOCK SOURCE
0
PSR321
R/W
0
0
clk
T1
(1)
SFIOR
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