FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 69

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

1. The GAP2 written to a perpendicular drive
2. The write pre-compensation given to a
3. For
Note: Bits D0-D3 can only be overwritten when
during a write operation will depend upon the
programmed data rate.
perpendicular mode drive will be 0ns.
conventional mode drives any data written
will be at the currently programmed write
pre-compensation.
OW is programmed as a "1".If either
WGATE
D0-D3
0
0
1
1
GAP
programmed
0
1
0
1
TABLE 32 - EFFECTS OF WGATE AND GAP BITS
Conventional
Perpendicular
(500 Kbps)
Reserved
(Conventional)
Perpendicular
(1 Mbps)
MODE
to
"0"
LENGTH OF GAP2
FORMAT FIELD
for
22 Bytes
22 Bytes
22 Bytes
41 Bytes
69
Software
following
MODE COMMAND:
1. "Software" resets (via the DOR or DSR
2. "Hardware" resets will clear all bits
registers) will only clear GAP and WGATE
bits to "0". D0-D3 are unaffected and retain
their previous value.
(GAP, WGATE and D0-D3) to "0", i.e all
conventional mode.
GAP or WGATE is a "1" then D0-D3 are
ignored.
effect
and
WRITTEN BY WRITE DATA
PORTION OF GAP 2
hardware
on
OPERATION
19 Bytes
38 Bytes
0 Bytes
0 Bytes
the
resets
PERPENDICULAR
have
the