FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 37

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

RESET
There are three sources of system reset on the
FDC: the RESET pin of the FDC, a reset
generated via a bit in the DOR, and a reset
generated via a bit in the DSR. At power on, a
Power On Reset initializes the FDC. All resets
take the FDC out of the power down state.
All operations are terminated upon a RESET,
and the FDC enters an idle state. A reset while
a disk write is in progress will corrupt the data
and CRC.
On exiting the reset state, various internal
registers are cleared, including the Configure
command information, and the FDC waits for a
new command. Drive polling will start unless
disabled by a new Configure command.
RESET Pin (Hardware Reset)
The RESET pin is a global reset and clears all
registers except those programmed by the
Specify command.
enabled and must be cleared by the host to exit
the reset state.
DOR Reset vs. DSR Reset (Software Reset)
These two resets are functionally the same.
BIT NO.
1,0
7
6
5
4
3
2
WP
T0
HD
DS1,0
SYMBOL
The DOR reset bit is
Write
Protected
Track 0
Head
Address
Drive Select
TABLE 19 - STATUS REGISTER 3
NAME
Unused. This bit is always "0".
Indicates the status of the WP pin.
Unused. This bit is always "1".
Indicates the status of the TRK0 pin.
Unused. This bit is always "1".
Indicates the status of the HDSEL pin.
Indicates the status of the DS1, DS0 pins.
37
Both will reset the FDC core, which affects drive
status information and the FIFO circuits. The
DSR reset clears itself automatically while the
DOR reset requires the host to manually clear it.
DOR reset has precedence over the DSR reset.
The DOR reset is set automatically upon a pin
reset. The user must manually clear this reset
bit in the DOR to exit the reset state.
MODES OF OPERATION
The FDC has three modes of operation, PC/AT
mode, PS/2 mode and Model 30 mode. These
are determined by the state of the IDENT and
MFM bits 3 and 2 respectively of LD8CRF0.
PC/AT mode - (IDENT high, MFM a "don't
care")
The PC/AT register set is enabled, the DMA
enable bit of the DOR becomes valid (FINTR
and DRQ can be hi Z), and TC and DENSEL
become active high signals.
PS/2 mode - (IDENT low, MFM high)
This mode supports the PS/2 models 50/60/80
configuration and register set. The DMA bit of
the DOR becomes a "don't care", (FINTR and
DRQ are always valid), TC and DENSEL
become active low.
DESCRIPTION