FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 142

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

the output will be undefined. The UIP (update in
progress) status bit is set during the interval.
When the UIP bit goes high, the update cycle
will begin 244 s later. Therefore, if a low is read
CONTROL AND STATUS REGISTERS, BANK
0
REGISTER A (AH)
UIP
The update in progress bit is a status flag that
may be monitored by the program. When UIP is
a "1" the update cycle is in progress or will soon
begin. When UIP is a "0" the update cycle is not
in progress and will not be for at least 244 s.
The time, calendar, and alarm information is
fully available to the program when the UIP bit is
zero. The UIP bit is a read- only bit and is not
affected by RESET_DRV. Writing the SET bit in
Register B to a "1" inhibits any update cycle and
then clears the UIP status bit. The UIP bit is
only valid when the RTC is enabled. Refer to
Table 66.
DV2-0
Three bits are used to permit the program to
select various conditions of the 22-stage divider
chain.
combinations.
MSB
UIP
INPUT CLOCK
b7
FREQUENCY
32.768 kHz
32.768 kHz
Table
DV2
The divider selection bits are
66
b6
shows
DV1
b5
the
UIP BIT
Table 65 - Update Cycle Time
1
0
allowable
DV0
b4
142
UPDATE CYCLE TIME
on the UIP bit, the user has at least 244
before time/calendar data will be changed.
Bank 0 of the RTC has five registers that are
accessible to the processor program at all times
when Bank 0 is enabled, even during the update
cycle. Note Register D, Bits[6:0] are not
accessible during an update cycle.
also used to reset the divider chain. When the
time/calendar is first initialized, the program
may start the divider chain at the precise time
stored in the registers. When the divider reset is
removed the first update begins one-half second
later. These three read/write bits are not affected
by RESET_DRV.
RS3-0
The four rate selection bits select one of 15 taps
on the divider chain or disable the divider
output. The selected tap determines rate or
frequency of the periodic interrupt. The program
may enable or disable the interrupt with the PIE
bit in Register B. Table 67 lists the periodic
interrupt rates and equivalent output frequencies
that may be chosen with the RS0-RS3 bits.
These four bits are read/write bits, which are not
affected by RESET_DRV.
RS3
b3
1948 s
-
RS2
b2
UPDATE CYCLE
RS1
MINIMUM TIME
b1
244 s
-
RS0
LSB
b0
s