FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 155

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

ACPI/PME/SMI REGISTERS
Logical Device A in the configuration section
contains the address pointer to the ACPI power
management register block, and PM1_BLK.
These are run-time registers; Included in the
PM1_BLK is an enable bit to allow the SCI
group interrupt to be routed to any serial
interrupt or the IRQ11 pin, or onto the
nPME/SCI pin.
register for SCI/PME/SMI selection function and
pin configuration bits.
Register Description
The ACPI register model consists of a number
of fixed register blocks that perform designated
functions. A register block consists of a number
of registers that perform Status, Enable and
Control functions. The ACPI specification deals
with events (which have an associated interrupt
status and enable bits, and sometimes an
associated
features. The status registers illustrate what
defined function is requesting ACPI interrupt
services (SCI). Any status bit in the ACPI
specification has the following attributes:
A.
B.
C.
D.
Status bits are only set through some
defined “hardware event.”
Unless otherwise noted, Status bits are
cleared by writing a “HIGH” to that bit
position, and upon VTR POR. Writing
a 0 has no effect.
Status bits only generate interrupts
while their associated bit in the enable
register is set.
Function bit positions in the status
register have the same bit position in
the
exceptions to this rule, special status
bits have no enables).
control
enable
Note: See IRQ mux control
function)
register
and
(there
control
are
155
Note that this implies that if the respective
enable bit is reset and the hardware event
occurs, the respective status bit is set, however
no interrupt is generated until the enable bit is
set. This allows software to test the state of the
event (by examining the status bit) without
necessarily generating an interrupt. There are a
special class of status bits that have no
respective enable bit, these are called out
specifically, and the respective enable bit in the
enable register is marked as reserved for these
special cases.
The enable registers allow the setting of the
status bit to generate an interrupt. As a general
rule there is an enable bit in the enable register
for every status bit in the status register. The
control register provides special controls for the
associated event, or special control features that
are not associated with an interrupt event. The
ordering of a register block is the status
registers, followed by enable registers, followed
by control registers.
TABLE 68 and TABLE 69 list the PM1/GPE and
PME/SMI/MSC register blocks and the locations
of the registers contained in these blocks. All of
these registers are powered by VTR and battery
backed-up and are reset on Vbat POR.
Wakeup Event Configuration is Retained by
Battery Power
To preserve the configuration of the wakeup
functions that were programmed prior to the
loss of Vtr upon its return, the soft power
management registers, PME, SCI, SMI registers
and GPIO registers are all powered by the
battery.
default values only on Vbat POR.
registers are described in the sections below.
These registers are reset to their
These