FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 132

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

normal reset sequence is initiated and program
execution starts from program memory location
0.
Hard Power Down Mode
Hard Power Down Mode is entered by executing
a STOP instruction. Disabling the oscillator
driver cell stops the oscillator. When either
RESET is driven active or a data byte is written
to the DBBIN register by a master CPU, this
mode will be exited (as above). However, as the
oscillator cell will require an initialization time,
either RESET must be held active for sufficient
time to allow the oscillator to stabilize. Program
execution will resume as above.
INTERRUPTS
The
interrupts, the IBF and the Timer/Counter
Overflow.
UD
D7
FDC37B78x
UD
D6
provides
UD
D5
the
TABLE 59 - STATUS REGISTER
two
UD
D4
8042
132
MEMORY CONFIGURATIONS
The FDC37B78x provides 2K of on-chip ROM
and 256 bytes of on-chip RAM.
Register Definitions
Host I/F Data Register
The Input Data and Output Data registers are
each 8 bits wide. A write to this 8 bit register will
load the Keyboard Data Read Buffer, set the
OBF flag and set the KIRQ output if enabled. A
read of this register will read the data from the
Keyboard Data or Command Write Buffer and
clear the IBF flag. Refer to the KIRQ and Status
register descriptions for more information.
Host I/F Status Register
The Status register is 8 bits wide. TABLE 59
shows the contents of the Status register.
C/D
D3
UD
D2
IBF
D1
OBF
D0