FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 157

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

ACPI REGISTERS
In the FDC37B78x, the PME wakeup events can be enabled as SCI events through the SCI_STS1 and
SCI_EN1 bits in the GPE status and enable registers. See PME Interface and SMI/PME/SCI logic
sections.
Power Management 1 Status Register 1 (PM1_STS 1)
Register Location: <PM1_BLK> System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
Note 0: All bits described as "reserved" in writeable registers must be written with the value 0 when the
register is written.
Note 1: This bit is set by hardware and can only be cleared by software writing a one to this bit
position and by Vbat POR. Writing a 0 has no effect.
Power Management 1 Status Register 2 (PM1_STS 2)
Register Location: <PM1_BLK>+1h System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
0
1
2
0-7
BIT
BIT
Reserved
PWRBTN_STS
Reserved
RTC_STS
NAME
NAME
This bit is set when the Button_In signal is asserted. In the system
working state, while PWRBTN_EN and PWRBTN_STS are both set
an SCI interrupt event is raised. In the sleeping or soft off state, a
wake-up event is generated (regardless of the setting of
PWRBTN_EN) (Note 2). This bit is only set by hardware and is
reset by software writing a one to this bit position, and by Vbat
POR. Writing a 0 has no effect. It is also reset as follows: If
PWRBTNOR_EN is set, and if the Button_In signal is held
asserted for more than four seconds, then this bit is cleared, the
PWRBTNOR_STS bit is set and the system will transition into the
soft off state (nPowerOn floats).
Reserved.
This bit is set when the RTC generates an alarm. Additionally if the
RTC_EN bit is set then the setting of the RTC_STS bit will generate
an SCI. When the AL_REM_EN bit is set in the RTC control
register 1, then the RTC_STS bit is set due to an RTC alarm event
occurring when Vtr is not present. This will indicate to the OS the
cause of the wakeup event (nPowerOn pin asserted when Vtr
returns) caused by the “alarm remember” logic in the Soft Power
Management block. (Note 1)
Reserved. These bits always return a value of zero.
157
DESCRIPTION
DESCRIPTION