FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 159

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

Power Management 1 Control Register 1 (PM1_CNTRL 1)
Register Location: <PM1_BLK>+4 System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
Power Management 1 Control Register 2 (PM1_CNTRL 2)
Register Location: <PM1_BLK>+5 System I/O Space
Default Value: 00h on Vbat POR
Attribute: Read/Write (Note 0)
Size: 8-bits
BIT
2-4
6-7
BIT
0
1
5
1-7
0
Reserved
PWRBTNOR_E
N
SLP_TYPx
SLP_EN
Reserved
SCI_EN
Reserved
NAME
NAME
When this bit is set, then the SCI enabled power management events will
generate an SCI interrupt. When this bit is reset power management
events will not generate an SCI interrupt.
Reserved. These bits always return a value of zero.
Reserved. This field always returns zero.
This bit controls the power button over-ride function. When set, then
anytime the Button_In signal is asserted for more than four seconds
the system will transition to the off state. When a power button over-
ride event occurs, the logic should clear the PWRBTN_STS bit, and
set the PWRBTNOR_STS bit.
This 3-bit field defines the type of hardware sleep state the system
enters when the SLP_EN bit is set to one. When this field is 000 the
FDC37B78x will transition the machine to the off state when the
SLP_EN bit is set to one. That is, with this field set to 000, nPowerOn
will go inactive (float) after a 1-2 RTC clock delay when SLP_EN is
set. This delay is a minimum of one 32kHz clock and a maximum of
two 32kHz clocks (31.25 sec-62.5 sec). When this field is any other
value, there is no effect.
This is a write-only bit and reads to it always return a zero. Writing ‘1’
to this bit causes the system to sequence into the sleeping state
associated with the SLP_TYPx fields after a 1-2 RTC clock delay, if
the SLP_CTRL bit in the sleep / wake configuration register (0xF0 in
Logical Device A) is cleared. If the SLP_CTRL bit is set, do not
sequence into the sleeping state associated with the SLP_TYPx field,
but generate an SMI. Note: the SLP_EN_SMI bit in the SMI Status
Register 2 is always set upon writing ‘1’ to the SLP_EN bit. Writing ‘0’
to this bit has no effect.
Reserved. This field always returns zero.
159
DESCRIPTION
DESCRIPTION