FDC37B78X SMSC Corporation, FDC37B78X Datasheet - Page 145

• Manufacturer Part Number: FDC37B78X
• Description: Enhanced Super I/O Controller with ACPI Support/ Real Time Clock and Consumer IR
• Manufacturer: SMSC Corporation

PF is set to a "1" independent of the state of
the PIE bit. PF being a "1" sets the IRQF bit
and initiates an IRQB signal when PIE is also a
"1". The PF bit is cleared by RESET_DRV or by
a read of Register C .
AF
The alarm interrupt flag when set to a "1"
indicates that the current time has matched the
alarm time. A "1" in AF causes a "1" to appear in
IRQF and the IRQB port to go low when the AIE
bit is also a "1". A RESET_DRV or a read of
Register C clears the AF bit.
VRT
When a "1", this bit indicates that the contents
of the RTC are valid. A "0" appears in the VRT
bit when the battery voltage is low. The VRT bit
is a read-only bit, which can only be set by a
read of Register D.
Management for the conditions when this bit is
reset. The processor program can set the VRT
bit when the time and calendar are initialized to
indicate that the time is valid.
b6
Read as zero and cannot be written.
XTAL_
CAP
D7
MSB
VRT
b7
REGISTER D (DH) - BITS[7,6] ARE READ-ONLY, BITS[5:0] ARE READ/WRITE
D6
0
b6
0
D5
0
Refer to Power
b5
D4
0
b4
145
UF
The update-ended interrupt flag bit is set after
each update cycle. When the UIE bit is also a
"1", the "1" in UF causes the IRQF bit to be set
and asserts IRQB. A RESET_DRV or a read of
Register C causes UF to be cleared.
b3-0
The unused bits of Register C are read as zeros
and cannot be written.
b5:b0
Date Alarm; These bits store the date of month
alarm value.
care state is assumed. The host must configure
the date alarm for these bits to do anything, yet
they can be written at any time.
alarm is not enabled, these bits will return zeros.
These bits are not affected by RESET_DRV.
Note: Bits[6:0] are not accessible during an
update cycle.
REGISTER 7E (7Eh) CONTROL REGISTER 1
Default is 0; cleared upon Vbat POR. This
register is battery backed-up.
D3
0
b3
Date Alarm
VTR_POR
_EN
D2
b2
If set to 000000b, then a don’t
VTR_POR
_OFF
D1
b1
AL_REM_
If the date
LSB
EN
D0
b0