LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 8

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 7-1.
Figure 8-1.
Figure 9-1.
Figure 9-2.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 11-1.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 303
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 304
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 304
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 14-5.
Figure 14-6.
Figure 14-7.
Figure 14-8.
Figure 14-9.
Figure 14-10. Master Burst RECEIVE .................................................................................................. 340
Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 341
Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 342
8
Stellaris
CPU Block Diagram ......................................................................................................... 34
TPIU Block Diagram ........................................................................................................ 35
JTAG Module Block Diagram ............................................................................................ 44
Test Access Port State Machine ....................................................................................... 47
IDCODE Register Format ................................................................................................. 52
BYPASS Register Format ................................................................................................ 53
Boundary Scan Register Format ....................................................................................... 53
External Circuitry to Extend Reset .................................................................................... 55
Hibernation Module Block Diagram ................................................................................. 113
Flash Block Diagram ...................................................................................................... 131
GPIODATA Write Example ............................................................................................. 156
GPIODATA Read Example ............................................................................................. 156
GPTM Module Block Diagram ........................................................................................ 196
16-Bit Input Edge Count Mode Example .......................................................................... 200
16-Bit Input Edge Time Mode Example ........................................................................... 201
16-Bit PWM Mode Example ............................................................................................ 202
WDT Module Block Diagram .......................................................................................... 231
UART Module Block Diagram ......................................................................................... 255
UART Character Frame ................................................................................................. 256
IrDA Data Modulation ..................................................................................................... 258
SSI Module Block Diagram ............................................................................................. 295
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 297
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 298
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 299
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 299
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 300
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 301
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 301
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 302
I
I
START and STOP Conditions ......................................................................................... 333
Complete Data Transfer with a 7-Bit Address ................................................................... 334
R/S Bit in First Byte ........................................................................................................ 334
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 337
Master Single RECEIVE ................................................................................................. 338
Master Burst SEND ....................................................................................................... 339
2
2
C Block Diagram ......................................................................................................... 332
C Bus Configuration .................................................................................................... 333
®
1000 Series High-Level Block Diagram ............................................................... 26
Preliminary
2
C Bus ............................................................... 334
October 09, 2007