LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 170

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

General-Purpose Input/Outputs (GPIOs)
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
GPIO Port H base: 0x4002.7000
Offset 0x420
Type R/W, reset -
170
Reset
Reset
Type
Type
Bit/Field
31:8
RO
RO
31
15
0
0
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore
no GPIO line is set to hardware control by default.
The commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL)
register (see page 170) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 180) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 181) have been set to 1.
Important:
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors,
and apply RST or power-cycle the part.
In addition, it is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This
can be avoided with a software routine that restores JTAG functionality based on an external or software
trigger.
RO
RO
30
14
0
0
reserved
Name
RO
RO
29
13
0
0
®
All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
microcontroller. If the program code loaded into flash immediately changes the JTAG
RO
RO
28
12
0
0
reserved
RO
RO
Type
27
11
0
0
RO
RO
RO
26
10
0
0
Reset
0x00
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
RO
24
0
8
0
reserved
R/W
RO
23
0
7
-
R/W
RO
22
0
6
-
R/W
RO
21
0
5
-
R/W
RO
20
0
4
-
AFSEL
R/W
RO
19
0
3
-
R/W
RO
18
0
2
-
October 09, 2007
R/W
RO
17
0
1
-
R/W
RO
16
0
0
-