LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 428

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Signal Tables
428
Table 18-2. Signals by Signal Name
Pin Number
100
90
91
92
93
94
95
96
97
98
99
Pin Name
CMOD0
CMOD1
CCP0
CCP1
CCP2
CCP3
CCP4
CCP5
C0+
C0-
C0o
C1+
C1-
C1o
GND
GND
GND
Pin Name
GNDA
VDDA
CCP1
PB6
C0+
PB5
C1-
PB4
C0-
VDD
GND
PD4
PD5
PD6
PD7
Pin Number
100
90
92
24
24
91
66
67
23
22
25
65
76
15
21
2
9
Preliminary
Pin Type
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
-
-
-
-
-
-
-
I
I
I
I
I
I
I
Buffer Type
Buffer Type
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Power
Power
Power
Power
Power
Power
Power
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Description
GPIO port B bit 6
Analog comparator 0 positive input
GPIO port B bit 5
Analog comparator 1 negative input
GPIO port B bit 4
Analog comparator 0 negative input
Positive supply for I/O and some logic.
Ground reference for logic and I/O pins.
GPIO port D bit 4
GPIO port D bit 5
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
The positive supply (3.3 V) for the analog
circuits (ADC, Analog Comparators, etc.).
These are separated from VDD to minimize
the electrical noise contained on VDD from
affecting the analog functions.
GPIO port D bit 6
GPIO port D bit 7
Capture/Compare/PWM 1
Description
Analog comparator 0 positive input
Analog comparator 0 negative input
Analog comparator 0 output
Analog comparator positive input
Analog comparator 1 negative input
Analog comparator 1 output
Capture/Compare/PWM 0
Capture/Compare/PWM 1
Capture/Compare/PWM 2
Capture/Compare/PWM 3
Capture/Compare/PWM 4
Capture/Compare/PWM 5
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
October 09, 2007