LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 18
LM3S6611-IQC20-A0T
Manufacturer Part Number
LM3S6611-IQC20-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S6611-IQC20-A0T.pdf
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About This Document
About This Document
Audience
About This Manual
Related Documents
Documentation Conventions
18
This data sheet provides reference information for the LM3S6611 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
This manual is intended for system software developers, hardware designers, and application
developers.
This document is organized into sections that correspond to each major feature.
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
■
■
The following related documents are also referenced:
■
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
This document uses the conventions shown in Table 1 on page 18.
Table 1. Documentation Conventions
Notation
General Register Notation
REGISTER
bit
bit field
offset 0xnnn
Register N
ARM® Cortex™-M3 Technical Reference Manual
ARM® CoreSight Technical Reference Manual
ARM® v7-M Architecture Application Level Reference Manual
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
Meaning
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.
Two or more consecutive and related bits.
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 39.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Preliminary
October 09, 2007
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