LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 265

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Write-Only Error Clear (UARTECR) Register
UART Receive Status/Error Clear (UARTRSR/UARTECR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x004
Type WO, reset 0x0000.0000
October 09, 2007
Reset
Reset
Type
Type
Bit/Field
Bit/Field
31:8
7:0
1
0
WO
WO
31
15
0
0
WO
WO
30
14
0
0
reserved
Name
Name
DATA
PE
FE
WO
WO
29
13
0
0
WO
WO
28
12
0
0
reserved
WO
WO
Type
Type
27
11
0
0
WO
WO
RO
RO
WO
WO
26
10
0
0
Reset
Reset
0
0
0
0
WO
WO
25
0
9
0
Preliminary
Description
UART Parity Error
This bit is set to 1 when the parity of the received data character does
not match the parity defined by bits 2 and 7 of the UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
UART Framing Error
This bit is set to 1 when the received character does not have a valid
stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of
the FIFO.
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Error Clear
A write to this register of any data clears the framing, parity, break, and
overrun flags.
WO
WO
24
0
8
0
reserved
WO
WO
23
0
7
0
WO
WO
22
0
6
0
WO
WO
21
0
5
0
WO
WO
20
0
4
0
DATA
LM3S6611 Microcontroller
WO
WO
19
0
3
0
WO
WO
18
0
2
0
WO
WO
17
0
1
0
WO
WO
16
0
0
0
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