LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 346

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Inter-Integrated Circuit (I
I2C Master Slave Address (I2CMSA)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x000
Type R/W, reset 0x0000.0000
346
Reset
Reset
Type
Type
Bit/Field
31:8
7:1
0
RO
RO
31
15
0
0
Register 1: I
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).
RO
RO
30
14
0
0
reserved
Name
R/S
SA
RO
RO
29
13
0
0
2
C) Interface
2
RO
RO
28
12
0
0
C Master Slave Address (I2CMSA), offset 0x000
reserved
RO
RO
Type
27
11
R/W
R/W
0
0
RO
RO
RO
26
10
0
0
Reset
0x00
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I
This field specifies bits A6 through A0 of the slave address.
Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or Send
(Low).
0: Send
1: Receive
RO
RO
2
24
0
8
0
C Slave Address
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
SA
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
October 09, 2007
R/W
RO
17
0
1
0
R/W
R/S
RO
16
0
0
0