LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 127

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Hibernation Masked Interrupt Status (HIBMIS)
Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
October 09, 2007
Reset
Reset
Type
Type
Bit/Field
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C
This register is the masked interrupt status for the Hibernation module interrupt sources.
RO
RO
30
14
0
0
RTCALT1
RTCALT0
LOWBAT
reserved
EXTW
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
0x000.0000
reserved
Reset
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
External Wake-Up Masked Interrupt Status
Low Battery Voltage Masked Interrupt Status
RTC Alert1 Masked Interrupt Status
RTC Alert0 Masked Interrupt Status
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S6611 Microcontroller
EXTW
RO
RO
19
0
3
0
LOWBAT
RO
RO
18
0
2
0
RTCALT1
RO
RO
17
0
1
0
RTCALT0
RO
RO
16
0
0
0
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