LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 426
LM3S6611-IQC20-A0T
Manufacturer Part Number
LM3S6611-IQC20-A0T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S6611-IQC20-A0T.pdf
(477 pages)
- Current page: 426 of 477
- Download datasheet (5Mb)
Signal Tables
426
Pin Number
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Pin Name
GNDPHY
GNDPHY
VDD25
XOSC0
XOSC1
VDD25
CMOD0
RXIP
TXOP
TXON
OSC0
OSC1
WAKE
VBAT
MDIO
LED0
LED1
GND
VDD
GND
PF0
HIB
GND
VDD
GND
PF3
PF2
PF1
GND
RST
Preliminary
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
I
I
I
I
I
I
I
Buffer Type
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
OD
Description
Positive supply for most of the logic function,
including the processor core and most
peripherals.
Ground reference for logic and I/O pins.
RXIP of the Ethernet PHY
GND of the Ethernet PHY
GND of the Ethernet PHY
TXOP of the Ethernet PHY
Positive supply for I/O and some logic.
Ground reference for logic and I/O pins.
TXON of the Ethernet PHY
GPIO port F bit 0
Main oscillator crystal input or an external
clock reference input.
Main oscillator crystal output.
An external input that brings the processor out
of hibernate mode when asserted.
An output that indicates the processor is in
hibernate mode.
Hibernation Module oscillator crystal input or
an external clock reference input. Note that
this is either a 4.19-MHz crystal or a
32.768-kHz oscillator for the Hibernation
Module RTC. See the CLKSEL bit in the
HIBCTL register.
Hibernation Module oscillator crystal output.
Ground reference for logic and I/O pins.
Power source for the Hibernation Module. It
is normally connected to the positive terminal
of a battery and serves as the battery
backup/Hibernation Module power-source
supply.
Positive supply for I/O and some logic.
Ground reference for logic and I/O pins.
MDIO of the Ethernet PHY
GPIO port F bit 3
MII LED 0
GPIO port F bit 2
MII LED 1
GPIO port F bit 1
Positive supply for most of the logic function,
including the processor core and most
peripherals.
Ground reference for logic and I/O pins.
System reset input.
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
October 09, 2007
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