LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 123

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Hibernation Control (HIBCTL)
Base 0x400F.C000
Offset 0x010
Type R/W, reset 0x0000.0000
October 09, 2007
Reset
Reset
Type
Type
Bit/Field
31:8
7
6
5
4
3
RO
RO
31
15
0
0
Register 5: Hibernation Control (HIBCTL), offset 0x010
This register is the control register for the Hibernation module.
RO
RO
30
14
0
0
LOWBATEN
CLK32EN
RTCWEN
reserved
VABORT
PINWEN
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
Type
27
11
R/W
R/W
R/W
R/W
R/W
0
0
RO
RO
RO
26
10
0
0
Reset
0x00
0
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power Cut Abort Enable
0: Power cut occurs during a low-battery alert
1: Power cut is aborted
32-kHz Oscillator Enable
0: Disabled
1: Enabled
This bit must be enabled to use the Hibernation module. If a crystal is
used, then software should wait 20 ms after setting this bit to allow the
crystal to power up and stabilize.
Low Battery Monitoring Enable
0: Disabled
1: Enabled
When set, low battery voltage detection is enabled.
External WAKE Pin Enable
0: Disabled
1: Enabled
When set, an external event on the WAKE pin will re-power the device.
RTC Wake-up Enable
0: Disabled
1: Enabled
When set, an RTC match event (RTCM0 or RTCM1) will re-power the
device based on the RTC counter value matching the corresponding
match register 0 or 1.
RO
RO
24
0
8
0
reserved
VABORT
R/W
RO
23
0
7
0
CLK32EN
R/W
RO
22
0
6
0
LOWBA TEN
R/W
RO
21
0
5
0
PINWEN
R/W
RO
20
0
4
0
RTCWEN
LM3S6611 Microcontroller
R/W
RO
19
0
3
0
CLKSEL
R/W
RO
18
0
2
0
HIBREQ
R/W
RO
17
0
1
0
RTCEN
R/W
RO
16
0
0
0
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