LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 262

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Universal Asynchronous Receivers/Transmitters (UARTs)
UART Data (UARTDR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x000
Type R/W, reset 0x0000.0000
262
Reset
Reset
Type
Type
Bit/Field
31:12
11
10
RO
RO
31
15
0
0
Register 1: UART Data (UARTDR), offset 0x000
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity,
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data can be retrieved by reading this register.
RO
RO
30
14
0
0
reserved
reserved
Name
OE
BE
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
OE
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
BE
26
10
0
0
Reset
0
0
0
RO
RO
PE
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error
The OE values are defined as follows:
UART Break Error
This bit is set to 1 when a break condition is detected, indicating that
the receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into the
FIFO. The next character is only enabled after the received data input
goes to a 1 (marking state) and the next valid start bit is received.
RO
RO
Value
FE
24
0
8
0
reserved
0
1
Description
There has been no data loss due to a FIFO overrun.
New data was received when the FIFO was full, resulting in
data loss.
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
DATA
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
October 09, 2007
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0