LM3S6611-IQC20-A0T ETC2 [List of Unclassifed Manufacturers], LM3S6611-IQC20-A0T Datasheet - Page 117

• Manufacturer Part Number: LM3S6611-IQC20-A0T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

7.3.4
7.3.5
7.4
Table 7-1. Hibernation Module Register Map
October 09, 2007
0x030-
Offset
0x00C
0x01C
0x12C
0x000
0x004
0x008
0x010
0x014
0x018
0x020
0x024
Name
HIBRTCC
HIBRTCM0
HIBRTCM1
HIBRTCLD
HIBCTL
HIBIM
HIBRIS
HIBMIS
HIBIC
HIBRTCT
HIBDATA
4.
External Wake-Up from Hibernation
The following steps are needed to use the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
1.
2.
RTC/External Wake-Up from Hibernation
1.
2.
3.
4.
Register Map
Table 7-1 on page 117 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000.
Note:
Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.
Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the
HIBCTL register at offset 0x010.
Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and require a delay of t
accesses. See “Register Access Timing” on page 113.
R/W1C
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
0xFFFF.FFFF
0xFFFF.FFFF
0xFFFF.FFFF
0x0000.7FFF
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Reset
Preliminary
Description
Hibernation RTC Counter
Hibernation RTC Match 0
Hibernation RTC Match 1
Hibernation RTC Load
Hibernation Control
Hibernation Interrupt Mask
Hibernation Raw Interrupt Status
Hibernation Masked Interrupt Status
Hibernation Interrupt Clear
Hibernation RTC Trim
Hibernation Data
HIB_REG_WRITE
LM3S6611 Microcontroller
between write
page
See
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120
121
122
123
125
126
127
128
129
130
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