MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 592
MC9S12G
Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12G.pdf
(1160 pages)
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Serial Communication Interface (S12SCIV5)
In
perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data
recovery is successful.
In
at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived
bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
592
Figure
Figure
RT Clock Count
Reset RT Clock
RT Clock Count
Reset RT Clock
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
RT Clock
RT Clock
Samples
Samples
18-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample
18-23, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the
RXD
RXD
1
1
1
1
1
1
1
0
1
Figure 18-22. Start Bit Search Example 1
Figure 18-23. Start Bit Search Example 2
0
MC9S12G Family Reference Manual,
1
1
1
1
0
0
Perceived Start Bit
0
0
0
0
0
0
Actual Start Bit
Start Bit
0
Rev.1.01
0
0
0
Freescale Semiconductor
LSB
LSB
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