MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 300

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12S Debug Module (S12SDBG)
8.4.2
The DBG contains three comparators, A, B and C. Each comparator compares the system address bus with
the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparator A also compares
the data buses to the data stored in DBGADH, DBGADL and allows masking of individual data bus bits.
All comparators are disabled in BDM and during BDM accesses.
The comparator match control logic (see
exact address or an address range, whereby either an access inside or outside the specified range generates
a match condition. The comparator configuration is controlled by the control register contents and the
range control by the DBGC2 contents.
A match can initiate a transition to another state sequencer state (see
Control”). The comparator control register also allows the type of access to be included in the comparison
through the use of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write
comparison is enabled for the associated comparator and the RW bit selects either a read or write access
for a valid match. Similarly the SZE and SZ bits allow the size of access (word or byte) to be considered
in the compare. Only comparators A and B feature SZE and SZ.
The TAG bit in each comparator control register is used to determine the match condition. By setting TAG,
the comparator qualifies a match with the output of opcode tracking logic and a state sequencer transition
occurs when the tagged instruction reaches the CPU execution stage. Whilst tagging the RW, RWE, SZE,
and SZ bits and the comparator data registers are ignored; the comparator address register must be loaded
with the exact opcode address.
If the TAG bit is clear (forced type match) a comparator match is generated when the selected address
appears on the system address bus. If the selected address is an opcode address, the match is generated
300
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
TAGHITS
SECURE
CPU BUS
READ TRACE DATA (DBG READ DATA BUS)
Comparator Modes
COMPARATOR A
COMPARATOR C
COMPARATOR B
MC9S12G Family Reference Manual,
Figure 8-23. DBG Overview
Figure
8-23) configures comparators to monitor the buses for an
MATCH1
MATCH2
MATCH0
CONTROL
MATCH
LOGIC
TAG &
Rev.1.01
Section 8.4.4, “State Sequence
TRANSITION
STATE
BREAKPOINT REQUESTS
TO CPU
TRACE BUFFER
TAGS
STATE SEQUENCER
Freescale Semiconductor
STATE
TRACE
CONTROL
TRIGGER