MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 406

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Analog-to-Digital Converter (ADC10B12CV2)
12.3.2.4
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
406
Module Base + 0x0003
S8C, S4C,
S2C, S1C
Reset
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
DJM
6–3
7
W
R
DJM
Result Register Data Justification — Result data format is always unsigned. This bit controls justification of
conversion data in the result registers.
0 Left justified data in the result registers.
1 Right justified data in the result registers.
Table 12-9
Conversion Sequence Length — These bits control the number of conversions per sequence.
shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity
to HC12 family.
ATD Control Register 3 (ATDCTL3)
0
7
gives example ATD results for an input signal range between 0 and 5.12 Volts.
S8C
= Unimplemented or Reserved
0
6
ETRIGLE
Figure 12-6. ATD Control Register 3 (ATDCTL3)
0
0
1
1
Table 12-7. External Trigger Configurations
MC9S12G Family Reference Manual,
Table 12-8. ATDCTL3 Field Descriptions
S4C
5
1
ETRIGP
0
1
0
1
S2C
0
4
Description
External Trigger Sensitivity
S1C
0
3
Falling edge
Rising edge
High level
Low level
Rev.1.01
FIFO
2
0
Freescale Semiconductor
FRZ1
0
1
Table 12-10
FRZ0
0
0