MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 193

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
1
2.4.3.41
2.4.3.42
Freescale Semiconductor
Address 0x0268 (G1, G2)
Address 0x0268 (G3)
Read: Anytime
Write: Anytime, write 1 to clear
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Field
PIFP
Reset
Reset
7-0
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
W
R
R
Port P interrupt flag—
If the associated interrupt enable bit is set this flag asserts after a valid active edge was detected on the related pin
(see
polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
PTJ7
Reserved Registers
Port J Data Register (PTJ)
0
0
0
7
7
Section 2.5.4.2, “Pin Interrupts and
Addresses 0x0260-0x0261 are reserved for ACMP registers in
only. Refer to
Section 3.6.2.2, “ACMP Status Register
PTJ6
0
0
0
6
6
Section 3.6.2.1, “ACMP Control Register
Table 2-67. PIFP Register Field Descriptions
MC9S12G Family Reference Manual, Rev.1.01
Figure 2-42. Port J Data Register (PTJ)
PTJ5
0
0
0
5
5
Wakeup”). This can be a rising or a falling edge based on the state of the
PTJ4
0
0
0
4
4
NOTE
Description
(ACMPS)”.
PTJ3
PTJ3
0
0
3
3
(ACMPC)” and
PTJ2
PTJ2
2
0
2
0
Port Integration Module (S12GPIMV0)
G2
and
Access: User read/write
Access: User read/write
PTJ1
PTJ1
G3
0
0
1
1
PTJ0
PTJ0
0
0
0
0
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1