MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 1117
MC9S12G
Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12G.pdf
(1160 pages)
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In
A.14.2
In
Freescale Semiconductor
Conditions are 4.5 V < V
Table A-32
Num
Figure A-8
(CPOL = 1)
(CPOL = 0)
10
11
12
13
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
1
1
2
3
4
5
6
9
(Output)
NOTE: Not defined
(Input)
(Input)
MOSI
(Input)
(Input)
MISO
SCK
SCK
SS
C
D
D
D
D
D
D
D
D
D
D
D
D
Slave Mode
10
7
the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
the timing characteristics for master mode are listed.
SCK Frequency
SCK Period
Enable Lead Time
Enable Trail Time
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Data Valid after SCK Edge
Data Valid after SS fall (CPHA=0)
Data Hold Time (Outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
Note
See
DD35
2
5
MSB IN
< 5.5 V junction temperature from –40°C to +150°C.
Table A-32. SPI Master Mode Timing Characteristics
Characteristic
Slave MSB
6
4
MC9S12G Family Reference Manual, Rev.1.01
Figure A-8. SPI Slave Timing (CPHA = 0)
1
4
Bit MSB-1. . . 1
Bit MSB-1 . . . 1
9
12
12
Symbol
t
t
f
t
wsck
t
vsck
t
t
t
sck
sck
t
vss
t
t
t
ho
rfo
su
hi
rfi
T
L
11
Slave LSB OUT
LSB IN
1/2048
Min
—
—
—
—
—
—
—
2
8
8
0
13
13
11
3
Typ
1/2
1/2
1/2
—
—
—
—
—
—
—
—
—
Note
See
Electrical Characteristics
2048
Max
1/2
15
15
—
—
—
—
—
—
9
9
8
Unit
f
t
t
t
t
bus
bus
ns
ns
ns
ns
ns
ns
ns
sck
sck
sck
1117
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