MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 583
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MC9S12G
Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12G.pdf
(1160 pages)
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18.4.4
A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the
transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor.
The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is
synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the
transmitter. The receiver has an acquisition rate of 16 samples per bit time.
Baud rate generation is subject to one source of error:
Table 18-16
When IREN = 0 then,
Freescale Semiconductor
•
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Integer division of the bus clock may not give the exact target frequency.
SCI baud rate = SCI bus clock / (16 * SCIBR[12:0])
Baud Rate Generation
lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz.
SBR[12:0]
1302
2604
5208
Bits
163
326
651
41
81
Table 18-16. Baud Rates (Example: Bus Clock = 25 MHz)
MC9S12G Family Reference Manual, Rev.1.01
Clock (Hz)
609,756.1
308,642.0
153,374.2
Receiver
76,687.1
38,402.5
19,201.2
9600.6
4800.0
Transmitter
Clock (Hz)
38,109.8
19,290.1
9585.9
4792.9
2400.2
1200.1
600.0
300.0
Baud Rate
38,400
19,200
Target
9,600
4,800
2,400
1,200
600
300
Serial Communication Interface (S12SCIV5)
Error
(%)
.76
.47
.16
.15
.01
.01
.00
.00
583
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