MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 138
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MC9S12G
Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12G.pdf
(1160 pages)
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Port Integration Module (S12GPIMV0)
2.3.9
2.3.10
138
PM3
PM2
PM1
PM0
PP7-PP6
PP5-PP4
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Pins PM3-0
Pins PP7-0
• 64/100 LQFP: The SCI2 TXD signal is mapped to this pin when used with the SCI function. If the SCI2
• Signal priority:
• 64/100 LQFP: The SCI2 RXD signal is mapped to this pin when used with the SCI function. If the SCI2
• Signal priority:
• Except 20 TSSOP: The TXCAN signal is mapped to this pin when used with the CAN function. The
• 32 LQFP: The SCI1 TXD signal is mapped to this pin when used with the SCI function. If the SCI1 TXD
• 48 LQFP: The SCI2 TXD signal is mapped to this pin when used with the SCI function. If the SCI2 TXD
• Signal priority:
• Except 20 TSSOP: The RXCAN signal is mapped to this pin when used with the CAN function. The
• 32 LQFP: The SCI1 RXD signal is mapped to this pin when used with the SCI function. The enabled
• 48 LQFP: The SCI2 RXD signal is mapped to this pin when used with the SCI function. The enabled
• Signal priority:
• 64/100 LQFP: The PWM channels 7 and 6 signal are mapped to these pins when used with the PWM
• 64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
• 48/64/100 LQFP: The PWM channels 5 and 4 signal are mapped to these pins when used with the
• 48/64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
TXD signal is enabled the I/O state will depend on the SCI2 configuration.
64/100 LQFP: TXD2 > GPO
RXD signal is enabled the I/O state will be forced to be input.
64/100 LQFP: RXD2 > GPO
enabled CAN forces the I/O state to be an output.
signal is enabled the I/O state will depend on the SCI1 configuration.
signal is enabled the I/O state will depend on the SCI2 configuration.
32 LQFP: TXCAN > TXD1 > GPO
48 LQFP: TXCAN > TXD2 > GPO
64/100 LQFP: TXCAN > GPO
enabled CAN forces the I/O state to be an input. If CAN is active the selection of a pulldown device on
the RXCAN input has no effect.
SCI1 RXD signal forces the I/O state to an input.
SCI2 RXD signal forces the I/O state to an input.
32 LQFP: RXCAN > RXD1 > GPO
48 LQFP: RXCAN > RXD2 > GPO
64/100 LQFP: RXCAN > GPO
function. The enabled PWM channel forces the I/O state to be an output.
64/100 LQFP: PWM > GPO
PWM function. The enabled PWM channel forces the I/O state to be an output.
48/64/100 LQFP: PWM > GPO
MC9S12G Family Reference Manual,
Table 2-13. Port
Table 2-14. Port
M
P
Pins PM3-0
Pins PP7-0
Rev.1.01
Freescale Semiconductor
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