MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 561
MC9S12G
Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12G.pdf
(1160 pages)
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Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the
corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order
bytes PWMEx bits have no effect and their corresponding PWM output is disabled.
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Clock Source 7
Clock Source 5
Clock Source 3
Clock Source 1
MC9S12G Family Reference Manual, Rev.1.01
Figure 17-21. PWM 16-Bit Mode
PWMCNT6
PWMCNT4
PWMCNT2
PWMCNT0
High
High
High
High
Period/Duty Compare
Period/Duty Compare
Period/Duty Compare
Period/Duty Compare
PWMCNT7
PWMCNT5
PWMCNT3
PWMCNT1
Maximum possible 16-bit channels
Low
Low
Low
Low
Pulse-Width Modulator (S12PWM8B8CV2)
PWM7
PWM5
PWM3
PWM1
561
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