MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 159

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MC9S12G

Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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2.4.2.3
Freescale Semiconductor
Global Address
Global Address
0x000A–0x000B
0x000E–0x001B
0x0000–0x0007
Register Name
Register Name
Address Range
Address Range
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
ECLKCTL
Reserved
Reserved
Reserved
Non-PIM
Non-PIM
PIF0AD
PIF1AD
0x000C
0x000D
0x001C
0x001D
0x027E
0x027F
PORTE
0x0008
0x0009
DDRE
PUCR
Block Register Map (G3)
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
PIF0AD7
PIF1AD7
NECLK
Bit 7
Bit 7
0
0
0
0
0
0
Table 2-20. Block Register Map (G2) (continued)
MC9S12G Family Reference Manual, Rev.1.01
= Unimplemented or Reserved
= Unimplemented or Reserved
PIF0AD6
PIF1AD6
NCLKX2
BKPUE
Table 2-21. Block Register Map (G3)
6
6
0
0
0
0
0
PIF0AD5
PIF1AD5
DIV16
5
5
0
0
0
0
0
0
Non-PIM Address Range
Non-PIM Address Range
PIF0AD4
PIF1AD4
PDPEE
EDIV4
4
4
0
0
0
0
0
PIF0AD3
PIF1AD3
EDIV3
3
3
0
0
0
0
0
0
PIF0AD2
PIF1AD2
Port Integration Module (S12GPIMV0)
EDIV2
2
2
0
0
0
0
0
0
PIF0AD1
PIF1AD1
DDRE1
EDIV1
PE1
1
1
0
0
0
0
PIF0AD0
PIF1AD0
DDRE0
EDIV0
Bit 0
Bit 0
PE0
0
0
0
0
159

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