FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 54

• Manufacturer Part Number: FDC37B72X_07
• Description: 128 Pin Enhanced Super I/O Controller with ACPI Support
• Manufacturer: SMSC [SMSC Corporation]

has elapsed. If the host issues another command
before the head unloads, then the head settling
time may be saved between subsequent reads.
If the FDC detects a pulse on the nINDEX pin
twice without finding the specified sector (meaning
that the diskette's index hole passes through index
detect logic in the drive twice), the FDC sets the IC
code in Status Register 0 to
abnormal termination, sets the ND bit in Status
Register 1 to "1" indicating a sector not found, and
terminates the Read Data Command.
MT
0
1
0
1
0
1
N
1
1
2
2
3
3
TABLE 24 - EFFECTS OF MT AND N BITS
256 x 26 = 6,656
256 x 52 = 13,312
512 x 15 = 7,680
512 x 30 = 15,360
1024 x 8 = 8,192
1024 x 16 = 16,384
MAXIMUM TRANSFER
"01" indicating
CAPACITY
54
After reading the ID and Data Fields in each
sector, the FDC checks the CRC bytes. If a CRC
error occurs in the ID or data field, the FDC sets
the IC code in Status Register 0 to "01" indicating
abnormal termination, sets the DE bit flag in Status
Register 1 to "1", sets the DD bit in Status Register
2 to "1" if CRC is incorrect in the ID field, and
terminates the Read Data Command. Table 21
describes the effect of the SK bit on the Read
Data command execution and results. Except
where noted in Table 21, the C or R value of the
sector address is automatically incremented (see
Table 23).
26 at side 0 or 1
26 at side 1
15 at side 0 or 1
15 at side 1
8 at side 0 or 1
16 at side 1
FINAL SECTOR READ
FROM DISK