FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 148

• Manufacturer Part Number: FDC37B72X_07
• Description: 128 Pin Enhanced Super I/O Controller with ACPI Support
• Manufacturer: SMSC [SMSC Corporation]

Power Management 1 Enable Register 1 (PM1_EN 1)
Register Location:
Default Value:
Attribute:
Size:
0-7
Power Management 1 Enable Register 2 (PM1_EN 2)
Register Location:
Default Value:
Attribute:
Size:
0
1-7
Power Management 1 Control Register 1 (PM1_CNTRL 1)
Register Location:
Default Value:
Attribute:
Size:
0
1-7
BIT
BIT
BIT
Reserved
PWRBTN_EN
Reserved
SCI_EN
Reserved
NAME
NAME
NAME
<PM1_BLK>+2 System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
<PM1_BLK>+3 System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
<PM1_BLK>+4 System I/O Space
00h on Vbat POR
Read/Write (Note 0)
8-bits
Reserved. These bits always return a value of zero.
This bit is used to enable the assertion of the Button_In to
generate an SCI event. The PWRBTN_STS bit is set anytime
the Button_In signal is asserted. The enable bit does not
have to be set to enable the setting of the PWRBTN_STS bit
by the assertion of the Button_In signal.
Reserved. These bits always return a value of zero.
When this bit is set, then the enabled SCI power management
events generate an SCI interrupt. When this bit is reset power
management events do not generate an SCI interrupt.
Reserved. These bits always return a value of zero.
148
DESCRIPTION
DESCRIPTION
DESCRIPTION