FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 164

• Manufacturer Part Number: FDC37B72X_07
• Description: 128 Pin Enhanced Super I/O Controller with ACPI Support
• Manufacturer: SMSC [SMSC Corporation]

Notes
Note 0: CR22 Bit 5 is reset on Vtr POR only
Note 1: This register contains some bits which are read or write only.
Note 2: Register 60 is the high byte; 61 is the low byte. For example to set the primary base address to
Note 3: These configuration registers are powered by Vtr and battery backed up.
Note 4: The Activate bit for Logical Device A does not effect the generation of an interrupt (SCI).
Note 5: Bits[0,2-7] are cleared on a V
0x61
INDEX
0x60,
0x30
0x70
0xF0
(2)
1234h, write 12h into 60, and 34h into 61.
TYPE
R/W
R/W
R/W
R/W
RESET
HARD
0x00,
0x00
0x00
-
-
LOGICAL DEVICE A CONFIGURATION REGISTERS (ACPI)
Vcc POR
0x00,
0x00
0x00
-
-
CC
POR or RESET_DRV.
Vtr POR
0x00,
0x00
0x00
-
-
165
Vbat
POR
0x00
0x00
-
-
RESET
SOFT
0x00,
0x00
0x00
-
-
Activate
Primary Base I/O Address
PM1_BLK
Primary Interrupt Select
Sleep/Wake Configuration
CONFIGURATION
4
REGISTER
3
3