FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 125

• Manufacturer Part Number: FDC37B72X_07
• Description: 128 Pin Enhanced Super I/O Controller with ACPI Support
• Manufacturer: SMSC [SMSC Corporation]

GPIO OPERATION
The operation of the GPIO ports is illustrated in
purposes only and is not intended to suggest specific implementation details.
When a GPIO port is programmed as an input,
reading it through the GPIO data register latches
either the inverted or non-inverted logic value
present at the GPIO pin. Writing to a GPIO port
that is programmed as an input has no effect
(TABLE 54).
GPx_nIOW
GPx_nIOR
HOST OPERATION
SD-bit
WRITE
READ
Data Register
Transparent
D-TYPE
Q
D
Bit-n
GPIO
Q
D
FIGURE 4 - GPIO FUNCTION ILLUSTRATION
TABLE 54 - GPIO READ/WRITE BEHAVIOR
LATCHED VALUE OF GPIO PIN LAST WRITE TO GPIO DATA
NO EFFECT
0
1
GPIO INPUT PORT
GPIO
Configuration
Register bit-2 or 5
(GROUP INT. ENABLE)
125
FIGURE 4
When a GPIO port is programmed as an output,
the logic value or the inverted logic value that has
been written into the GPIO data register is output
to the GPIO pin. Reading from a GPIO port that is
programmed as an output returns the last value
written to the data register (TABLE 54).
GP Group Interrupts (1 or 2)
GPIO
Configuration
Register bit-1
(Polarity)
. Note:
1
REGISTER
BIT PLACED IN GPIO DATA
REGISTER
0
FIGURE 4
GPIO OUTPUT PORT
GPIO
Configuration
Register bit-0
(Input/Output)
is for illustration
GPIO
PIN