FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 169

• Manufacturer Part Number: FDC37B72X_07
• Description: 128 Pin Enhanced Super I/O Controller with ACPI Support
• Manufacturer: SMSC [SMSC Corporation]

Note 1: A logical device will be active and powered up according to the following equation:
Note:
Note 2. The activate bit for Logical Device 5 (Serial Port 2) is reset on Vtr POR only.
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).
DMA Channel Select
Default = 0x04
on Vcc POR or
Reset_Drv
32-Bit Memory Space
Configuration
Logical Device
Logical Device Config. (0xE0-0xFE) Reserved - Vendor Defined (see SMSC defined
Reserved
LOGICAL DEVICE
REGISTER
The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing
one sets or clears the other.
If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical
Device I/O map, then read or write is not valid and is ignored.
(0xA9-0xDF) Reserved - not implemented.
(0x76-0xA8) Reserved - not implemented.
(0x71,0x73)
(0x74,0x75)
ADDRESS
0xFF
Reserved - not implemented.
locations ignore writes and return zero when read.
Only 0x74 is implemented for FDC, Serial Port 2 and
Parallel port. 0x75 is not implemented and ignores
writes and returns zero when read. Refer to DMA
Channel Configuration.
locations ignore writes and return zero when read.
locations ignore writes and return zero when read.
Logical Device Configuration Registers)
Reserved
170
DESCRIPTION
These register
These register
These register
STATE
C
C
C
C