FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 27

• Manufacturer Part Number: FDC37B72X_07
• Description: 128 Pin Enhanced Super I/O Controller with ACPI Support
• Manufacturer: SMSC [SMSC Corporation]

An overrun or underrun will terminate the current
command and the transfer of data. Disk writes will
complete the current sector by generating a 00
FIFO THRESHOLD
FIFO THRESHOLD
FIFO THRESHOLD
EXAMPLES
EXAMPLES
EXAMPLES
15 bytes
15 bytes
15 bytes
2 bytes
8 bytes
2 bytes
8 bytes
2 bytes
8 bytes
1 byte
1 byte
1 byte
TABLE 15 - FIFO SERVICE DELAY
1 x 4 μs - 1.5 μs = 2.5 μs
2 x 4 μs - 1.5 μs = 6.5 μs
8 x 4 μs - 1.5 μs = 30.5 μs
15 x 4 μs - 1.5 μs = 58.5 μs
1 x 8 μs - 1.5 μs = 6.5 μs
2 x 8 μs - 1.5 μs = 14.5 μs
8 x 8 μs - 1.5 μs = 62.5 μs
15 x 8 μs - 1.5 μs = 118.5 μs
1 x 16 μs - 1.5 μs = 14.5 μs
2 x 16 μs - 1.5 μs = 30.5 μs
8 x 16 μs - 1.5 μs = 126.5 μs
15 x 16 μs - 1.5 μs = 238.5 μs
MAXIMUM DELAY TO SERVICING AT
MAXIMUM DELAY TO SERVICING AT
MAXIMUM DELAY TO SERVICING AT
27
500 Kbps DATA RATE
pattern and valid CRC. Reads require the host to
remove the remaining data so that the result
phase may be entered.
2 Mbps DATA RATE
1 Mbps DATA RATE