FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 182

• Manufacturer Part Number: FDC37B72X_07
• Description: 128 Pin Enhanced Super I/O Controller with ACPI Support
• Manufacturer: SMSC [SMSC Corporation]

Delay 2 Time Set
Register
Default = 0x00
on VTR POR
IRQ Mux Control
Register
Default = 0x00
on Vbat POR
NAME
REG INDEX
0XC0 R/W
0xB8 R/W
The following signals are latched to detect and hold
the soft power event (Type 1) (Note 1)
Bit[0] RXD1: UART 1 Receive Data; high to low
Bit[1] RXD2: UART 2 Receive Data; high to low
Bit[3] RING Status bit “RING_STS”; Latched, cleared
on read.
0= nRING input did not occur.
1= Ring indicator input occurred on the nRING pin
Bit[5:4] Reserved
The following signal is latched to detect and hold the
soft power event (Type 3) (Note 1) but the output of
the latch does not feed into the power down circuitry:
Bit[2] Button: Button pressed, Cleared by a read of
Bits[7:6] Reserved
This register is used to set Delay 2 (for Soft Power
Management) to a value from 500 msec to 32 sec.
The default value is 500msec. Engineering Note:
this delay is started if OFF_EN is enabled and
OFF_DLY was set and a Button Input comes in.
Bits[5:0] The value of these bits correspond to the
delay time as follows:
000000= 500msec min to 510msec max
000001= 1sec min to 1.01sec max
000010= 1.5sec min to 1.51sec max
000011= 2sec min to 2.01sec max
...
111111 = 32sec min to 32.01sec max
Bits[7:6] Reserved
This register is used to configure the IRQs, including
PME, SCI and SMI.
Bit[0] Serial/Parallel IRQs
0=Serial IRQs are used
1=Parallel IRQS are used
Note 1: This bit does not control the SCI or SMI
and, if enabled, caused the wakeup
(activated nPowerOn)
this register
transition on the pin, cleared by a read of
this register
transition on the pin, cleared by a read of
this register
183
DEFINITION
STATE
C