FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 146

• Manufacturer Part Number: FDC37B72X_07
• Description: 128 Pin Enhanced Super I/O Controller with ACPI Support
• Manufacturer: SMSC [SMSC Corporation]

ACPI Registers
In the FDC37B72x, the PME wakeup events can be enabled as SCI events through the SCI_STS1 and
SCI_EN1 bits in the GPE status and enable registers. See PME Interface and SMI/PME/SCI logic
sections.
Power Management 1 Status Register 1 (PM1_STS 1)
Register Location:
Default Value:
Attribute:
Size:
0-7
Note 1: This bit is set by hardware and can only be cleared by software writing a one to this bit position
BIT
and by Vbat POR. Writing a 0 has no effect.
Reserved
NAME
Read/Write (Note 0)
8-bits
<PM1_BLK> System I/O Space
00h on Vbat POR
Reserved. These bits always return a value of zero.
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DESCRIPTION