FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 180
FDC37B72X_07
Manufacturer Part Number
FDC37B72X_07
Description
128 Pin Enhanced Super I/O Controller with ACPI Support
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.FDC37B72X_07.pdf
(238 pages)
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Auxiliary I/O, Logical Device 8
Soft Power Enable
Register 1
Default = 0x00
on Vbat POR
Soft Power Enable
Register 2
Default = 0x80
on Vbat POR
NAME
Table 73 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]
REG INDEX
0xB0 R/W
0xB1 R/W
The following bits are the enables for the wake-up
function of the nPowerOn bit. When enabled,
these bits allow their corresponding function to turn
on power to the system.
1 = ENABLED
0 = DISABLED
Bit[0] SP_RI1: UART 1 Ring Indicator Pin
Bit[1] SP_RI2: UART 2 Ring Indicator Pin
Bit[2] SP_KDAT: Keyboard Data Pin
Bit[3] SP_MDAT: Mouse Data Pin
Bit[4] SP_GPINT1: Group Interrupt 1
Bit[5] SP_GPINT2: Group Interrupt 2
Bit[6] SP_IRRX2: IRRX2 Input Pin
Bit[7] Reserved
The following bits are the enables for the wake-up
function of the nPowerOn bit. When enabled,
these bits allow their corresponding function to turn
on power to the system.
1 = ENABLED
0 = DISABLED
Bit[0] SP_RXD1: UART 1 Receive Data Pin
Bit[1] SP_RXD2: UART 2 Receive Data Pin
Bit[2] Reserved
Bit[3] RING Enable bit “RING_EN”
1=Enable ring indicator on nRING pin as wakeup
function to activate nPowerOn.
0=Disable.
Bit[4] VTR_POR_OFF. Controls state of nPowerOn
after VTR POR.
1=the nPowerOn pin will go inactive (float) and the
machine will remain off when the VTR POR occurs.
Software must not set VTR_POR_OFF and
VTR_POR_EN at the same time.
0=the nPowerOn pin will remain in the state it was in
prior to the VTR POR (unless the VTR_POR_EN bit
is set).
Bit[5] Reserved
Bit[6] VTR_POR_EN. Controls state of nPowerOn
after VTR POR.
1= the nPowerOn pin will go active (low) and the
181
DEFINITION
STATE
C
C
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