FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 166

• Manufacturer Part Number: FDC37B72X_07
• Description: 128 Pin Enhanced Super I/O Controller with ACPI Support
• Manufacturer: SMSC [SMSC Corporation]

Device ID
Hard wired
= 0x4C
Device Rev
Hard wired
= 0x00
PowerControl
Default = 0x00.
on Vcc POR or
Reset_Drv
hardware signal.
Power Mgmt
Default = 0x00.
on Vcc POR or
Reset_Drv
hardware signal
OSC
Default = 0x04,
on Vcc POR or
Reset_Drv
hardware signal.
Chip Level
Vendor Defined
REGISTER
ADDRESS
0x22 R/W
0x23 R/W
0x24 R/W
0x20 R
0x21 R
0x25
A read only register which provides device identification.
Bits[7:0] = 0x4C when read
A read only register which provides device revision
information. Bits[7:0] = 0x00 when read
Bit[0] FDC Power
Bit[1] Reserved
Bit[2] Reserved
Bit[3] Parallel Port Power
Bit[4] Serial Port 1 Power
Bit[5] Serial Port 2 Power
Bit[6] Reserved
Bit[7] Reserved
= 0
= 1
Bit[0] FDC
Bit[1] Reserved
Bit[2] Reserved
Bit[3] Parallel Port
Bit[4] Serial Port 1
Bit[5] Serial Port 2
Bit[6] Reserved (read as 0)
Bit[7] Reserved (read as 0)
= 0
= 1
Bit[0] Reserved
Bit [1] PLL Control
= 0
= 1
Bits[3:2] OSC
= 01
= 10
= 00
= 11
Bit [6:4] Reserved, set to zero
Bit[7] IRQ8 Polarity
= 0
= 1
Reserved - Writes are ignored, reads return 0.
IRQ8 is active low
Power off or disabled
Power on or enabled
Intelligent Pwr Mgmt off
Intelligent Pwr Mgmt on
Osc is on, BRG clock is on.
Same as above (01) case.
Osc is on, BRG Clock Enabled.
Osc is off, BRG clock is disabled.
IRQ8 is active high
PLL is on (backward Compatible)
PLL is off
167
DESCRIPTION
STATE
C
C
C
C
C