FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 115

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FDC37B72X_07

Manufacturer Part Number
FDC37B72X_07
Description
128 Pin Enhanced Super I/O Controller with ACPI Support
Manufacturer
SMSC [SMSC Corporation]
Datasheet
SERIAL IRQ
The FDC37B72x supports serial interrupts to transmit interrupt information to the host system. The serial
interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
Timing Diagrams For IRQSER Cycle
PCICLK
IRQSER
Drive Source
A) Start Frame timing with source sampled a low pulse on IRQ1
PCICLK = 33Mhz_IN pin
IRQSER = SIRQ pin
1) Start Frame pulse can be 4-8 clocks wide.
IRQ1
SL
or
H
H=Host Control
SL=Slave Control
START
Host Controller
START FRAME
H
1
S=Sample
R
115
T
R=Recovery
T=Turn-around
IRQ0 FRAME IRQ1 FRAME
S
None
R
T
S
IRQ1
R
T
IRQ2 FRAME
S
None
R
T

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