LAN9115_05 SMSC [SMSC Corporation], LAN9115_05 Datasheet - Page 91

• Manufacturer Part Number: LAN9115_05
• Description: Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9115
5.3.20
5.3.21
BITS
BITS
29-8
31-0
7-0
31
30
DESCRIPTION
CSR Busy. When a 1 is written into this bit, the read or write operation is
performed to the specified MAC CSR. This bit will remain set until the
operation is complete. In the case of a read this means that the host can
read valid data from the data register. The MAC_CSR_CMD and
MAC_CSR_DATA registers should not be modified until this bit is cleared.
R/nW. When set, this bit indicates that the host is requesting a read
operation. When clear, the host is performing a write.
Reserved.
CSR Address. The 8-bit value in this field selects which MAC CSR will be
accessed with the read or write operation.
DESCRIPTION
MAC CSR Data. Value read from or written to the MAC CSR’s.
MAC_CSR_CMD – MAC CSR Synchronizer Command Register
This register is used to control the read and write operations with the MAC CSR’s
MAC_CSR_DATA – MAC CSR Synchronizer Data Register
This register is used in conjunction with the MAC_CSR_CMD register to perform read and write
operations with the MAC CSR’s
Offset:
Offset:
A4h
A8h
DATASHEET
91
Size:
Size:
32 bits
32 bits
TYPE
TYPE
R/W
R/W
R/W
SC
RO
Revision 1.1 (05-17-05)
00000000h
DEFAULT
DEFAULT
00h
0
0
-